Integrated circuit modular radar antenna



Dec 17, 1968 r: COOK; ET A1. 3,417,393

INTEGRATED CIRCUIT MODULAR RADAR ANTENNA Original Filed Sept. 18, 196410 Sheets-Sheet 1 INVENTDR HARRY F. COOKE 2m N I VINCENT JR.

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tmw mk mmkm e tokqm S1200 hummt mmm xuqmqwml United States Patent3,417,393 INTEGRATED CIRCUIT MODULAR RADAR ANTENNA Harry F. Cooke,Richardson, and Tom M. Hyltin and Britton T. Vincent, In, Dallas, Tex.,assignors to Texas Instruments Incorporated, Dallas, Tex., a corporationof Delaware Continuation of application Ser. No. 397,491, Sept. 18,1964. This application Oct. 18, 1967, Ser. No. 676,362

11 Claims. (Cl. 343-5) ABSTRACT OF THE DISCLOSURE A phased array radarsystem including an array of transmit-receive modules, and manifoldstructure for providing AC and DC power to the array and for summingoutput signals from each of the modules, each module including aradiation element and capable of providing power amplification, phaseshifting, mixing, and frequency multiplication of a transmitted and/orreceived signal in the module. Included also is a solid state mixer,frequency multiplier, phase shifter, power amplifier, and scan controlsystem for the radar.

This is a streamlined continuation of application Ser. No. 397,491,filed Sept. 18, 1964, now abandoned.

This invention relates to radar involving solid-state microwave modularantenna, and more particularly to modules forming a multi'element phasedarray antenna.

While this invention is immediately advantageous in connection withconstruction and operation of airborne radar, it has application toother radar systems such as those used for ground mapping, search anddetection, fire control, tracking, and navigation and may be programmedto operate in any one of the above modes or in several of such modes ona time-sharing basis.

Airborne radar systems have been faced with the problems of minimizingthe weight and increasing the reliability. Other problems involve thegeneration of high power microwave energy and the requirements forcomplex signal process and for computing circuitry. However, majorproblems in radar have been concerned with auxiliary equipment such asrotary joints, servo motors for the antennas, and the like. Restrictionsimposed by such components on reliability exist in the most modern ofall transistorized radars produced for airborne service. Further, theuse of magnetrons for transmitting, klystrons for local oscillatorservice, and use of high power transmit-receive (TR) protection devices,all have been found to restrict the relability of the system.

The present invention is directed to an improved radar antenna module inwhich solid-state circuitry is so constructed that a radar system basedthereon may overcome the major obstacles heretofore encountered in thedevelopment of solid-state radar, namely, the generation of high powermicrowave energy. This problem may be overcome by use of a solid-statefunctional electronic module for constructing a modular antenna arrayresponsive to beam steering control. Such modules may be operated at anadequate power level at X-band frequencies of, for example, 9 gc. (9x10cycles per second). A light-weight multi-element array antenna may beformed which uses electronic beam scanning and eliminates wave guides,rotary joints, motors, synchros, gears, and other servo componentsnormally essential to a scanning system. A substantial reduction intotal volume and weight over known or existing radars is achieved. Thisis accompanied by a substantial increase in the reliability of thesystem.

By the present invention, there is provided a solid-state transmittingand receiving module. Each individual antenna module with individualpower generation and phase control permits electronic beam steering. Theuse of soild-state modules, together with microwave transistors, permitsoperation in the X-band and higher, and thus permit operation in thatfrequency range required for airborne radar. While the modules arecapable of use in a wide variety of other radar and communicationinstallations, they are particularly suitable for airborne applications.Eliminated is the necessity for the magnetron, the local oscillatorklystron, and for high power TR protection devices.

Production of output power at the desired frequency involves use offrequency multipliers of integrated circuit construction. Frequencymultipliers in general are limited in their power handling capabilitiesby reason of the extremely small geometry necessary for operation athigh frequencies. The present invention involves a modular antenna withRF power generation, frequency multiplication and return signaldetection in each module.

In accordance with the present invention, a radar having an antennaformed of a multiplicity of modules forming a planar radiation arraytranslates a low-power pulsed RF carrier in each module to a pulse ofpower level suitable for antenna excitation.

More particularly, an amplifier for the RF carrier pulses amplifiers thepulses in each module to a power level exceeding that to be applied tothe antenna. A frequency-multiplier is connected for excitation of theantenna at a frequency substantially in excess of the frequency of thelow-power pulse of RF carrier. A receiver in each module produces areceived signal of electromagnetic energy reflected to the antennafollowing excitation thereof.

Phase control for the antenna excitation and for the received signal maybe carried out at low power levels. However, power amplification andfrequency multiplication are carried out in each antenna module withintegrated circuit construction which includes an integrated circuitmixer for the received signal in each module.

More particularly in accordance with the invention, a radar antenna isprovided having a manifold structure. An RF carrier channel, a phasecontrol carrier channel, a local oscillator signal channel, a DC. supplyvoltage channel, a plurality of reference voltage input channels and aplurality of IF output channels are included in the manifold. Aplurality of antenna modules are supported by the manifold and are allconnected to the RF carrier channel, the phase control carrier channel,the local oscillator channel, and the DC. supply voltage channel. Eachmodule is connected to one of the reference voltage input channels andto one the IF output channels.

In a more specific aspect, each modular structure supports a radiatingelement and includes a plurality of input lines and output lines. Afirst semiconductor integrated circuit mixer is connected at one inputto one input line. :An integrated circuit power amplifier circuit isconnected in a first signal channel extending between the mixer and theradiating element. A second integrated circuit mixer and IF preamplifierare connected in a second signal channel leading from the radiatingelement and the output line and is connected at one mixer input point toone of the input lines.

For a more complete understanding of the present invention and forfurther objects and advantages thereof, reference may now be had to thefollowing description taken in conjunction with the accompanyingdrawings in which:

FIGURE 1 diagrammatically illustrates the operation of an aircraft, itsantenna array, and the functional electronic block employed to make upthe array;

FIGURE 2 illustrates one form of a solid-state antenna module;

FIGURE 3 is a block diagram of the terrain-following radar of FIGURE 1;

FIGURE 4 is a block diagram of the electronics in each module;

FIGURE 5 is a top view of a solid-state mixer circuit of FIGURE 4comprising a surface-oriented diode, a strip transmission line, and acoupler;

FIGURE 6 is a sectional view taken along line 66 of FIGURE 5illustrating a planar alloy, surface-oriented diode;

FIGURE 7 is a modified form of surface-oriented diode in which diffusiontechniques are employed;

FIGURE 8 is a highly enlarged top view of the surfaceoriented diode;

FIGURE 9 illustrates preliminary steps in forming the diodeofFIGURE 7;

FIGURE 10 illustrates further processing steps in forming the diode ofFIGURE 7;

FIGURE 11 is a top view of the diode structure of FIGURE 10;

FIGURE 12 is a modified mixer construction employing a surface-orienteddiode wafer and ceramic substrate;

FIGURE 13 is a lumped constant diagram of the multiplier circuit ofFIGURE 4;

FIGURE 14 is a top view of an integrated circuit embodiment of themultiplier of FIGURE 13;

FIGURE 15 is a sectional view taken along lines 15-15 of FIGURE 14;

FIGURE 16 is an enlarged view of the fabrication sequence of the diodeof FIGURE 14 in planar form;

FIGURE 17 is an sectional view of a multiplier in which a mesa diode isemployed;

FIGURE 18 is a reactance vs. frequency diagram for the multipliercircuit;

FIGURE 19 illustrates a phase shift delay strip-line panel;

FIGURE 20 is a sectional view of the integrated circuit of one unit ofFIGURE 19 taken along lines 20-20;

FIGURE 21 illustrates video amplifier construction for the IFpreamplifier of FIGURE 4;

FIGURE 22 is a top view of antenna 12 illustrating beam-scanning;

FIGURE 23 is a schematic diagram illustrating distribution of referencevoltages to the antenna modules;

FIGURE 24 illustrates generation of reference voltages for the antennamodules; and

FIGURE 25 is a time plot of the sequence of operation of the radar ofFIGURE 4.

The invention will be described as it is employed in a terrain-followingradar. In this system, an aircraft 10 has an antenna unit 12 mounted inthe nose 13. Antenna unit 12 is comprised of a multiplicity offunctional electronic blocks, such as the block 14. In the exampleillustrated in FIGURE 1, 448 such blocks make up an antenna array ofoctagonal shape. The face of each block is of the order of one inch (1")square. Block 14 is adapted to be plugged into a suitable frame in theantenna unit 12 to transmit and receive electromagnetic energy by way ofslot 15.

The video information made available by the radar is then processed toprovide terrain-following capabilities. For example, in accordance withone mode of operation employed in a system known as the template system,a

' pre-master trigger is supplied to the template generator concurrentlywith each transmitted pulse from the antenna unit 12 to initiate asynthetic echo. This echo or template trigger occurs at a time rangethat is based upon the desired clearance altitude, the characteristicsof the air frame, and the scan position. The range of the templatetrigger changes with the scan angle. The scan angle is varied byadjusting the relative phase relationship between the microwave energyapplied to each of the modules in the antenna unit 12 during onevertical scan. The scan angle defines the template shape such asillustrated in FIGURE 1 by the outline 16. The video return or receivedsignals are compared with the synthetic echos to obtain proportionalcommand signals. The video return signal received before the syntheticecho signal is employed to generate climb commands. Similarly, the videoreturn signal received after the synthetic echo generates dive commands.

Use of the present invention involves a multi-element, phased antennaarray of solid-state construction capable of operation as above outlinedas well as in other modes. A new and unique structural and functionalrelationship between integrated semiconductor circuits is employed forantenna excitation and for beam steering any of a plurality of modes.

The modules of antenna unit 12 are of identical construction and may beof the character illustrated in FIG- URES 1 and"2, where a planar facemember 20 is provided with a slot 15 leading to microwave circuits whichare excited by pulses of an RF carrier of X-band frequency.

Antenna module 14 is unique in that it includes its own power generationcircuit and receiver preamplifier circuit and in addition has its ownphase shift circuit for beam steering. Included in the block 14 are aplurality of integrated circuits 24-29 which have the same grossappearance as units manufactured and sold by Texas InstrumentsIncorporated of Dallas, Tex., under the trademark Solid Circuits.

The size of the module is determined or limited by the allowable spacingbetween radiating elements for avoidance of spurious grating lobes.

System block diagram As shown in FIGURE 3, module 14 includes an RF unit30, a phase shift unit 31, and a control network 32. The phase shiftnetwork receives low-power RF carrier pulses by way of a channel 33 anddelivers output signals of IF frequency by way of channel 34. A beamsteering or phase control voltage is applied to the control network 32by way of channel 35. While only one module 14 has been shown in FIGURE3, it is to be understood that the 448 blocks illustrated in the antennaunit 12 of FIGURE 1 will similarly be excited and controlled from amanifold 40.

A source 41 supplies a pulsed RF carrier at 2.125 gc. to manifold 40under the control of a pulse compression generator 44. An oscillator 42supplies a pulsed phase control carrier at 125 me. to the manifold 40.As will hereinafter be explained, the phase control carrier is employedfor introducing a selected phase shift into the RF pulse from source 41.A local oscillator 43 applies a continuous low level voltage to manifold40 at a frequency of 8.5 gc.

Output signals at an IF frequency appear on channel 34 and are appliedfrom module 14 to manifold 40 for processing. As indicated, the IFsignals from modules in the upper quarter of the antenna unit 12 aresummed and appear on output channel 45. The sum of the IF output signalsfrom the upper center quarter of the antenna unit 12 appears on channel46. The sum of the IF output signals from the lower center quarter ofthe antenna unit 12 appears on channel 47, and corresponding signalsfrom the lower quarter of antenna unit 12 appear on output channel 48.

Channels 45 and 47 are connected to the inputs of a 3 db hybrid coupler50. The signals on channels 46 and 48 are applied to the inputs of acoupler 51. One output from coupler 50 is applied to a coupler 52 by wayof a 45 phase delay unit 53. The second input to coupler 52 is suppliedby one output of coupler 51. In a similar manner, a fourth coupler 54 issupplied by way of a phase delay unit 55 and by coupler 50. The outputsignals from couplers 52 and 54 are applied to IF amplifiers 56 and 57,respectively, which in turn feed pulse compression filters 58 and 59.Detectors 60 are driven by output signals from filters 58 and 59 and inturn drive a monopulse resolution improvement processor and videoamplifier 61. A signal recognition circuit 62 excited by unit 61 drivesa command computer 63, one output of which may be applied by way of aconverter 64 to an auto pilot 65.

An automatic gain control (AGC) 66 excited by the output of unit 61,controls 1F amplifiers 56 and 57. A sensitivity time control (STC) unit67 also feeds IF amplifiers 56 and 57 under the control of a timersynchronizer 68. Synchronizer 68 also feeds the command computer, as docommand input function generators 69-73. Generator 69 is a scan computerindicating the direction of the antenna beam. If an objective ispresent, then the system generates a control signal for autopilot 65.Generator 70 provides a signal representative of velocity of theaircraft. Generator 71 generates a signal representative of the actualflight vector. Generator 72 is a ride control generator, and determineswhether a rough or smooth course is followed, i.e., how abruptly theaircraft will change attitude when a target or obstacle is sensed.Generator 73 generates a signal representative of the aircraft pitchangle.

In the light of the foregoing description and with a knowledge of thevarious modes of operation of radar, it will be recognized that exactingrequirements are placed upon the elements to be included in module 14.In order to provide antenna power at the level necessary, solidstatecircuits are employed with circuit configurations such that thenecessary power may be supplied to the antenna and the desiredversatility and control thereof are available within the capabilities ofsolid-state semiconductor networks.

Antenna module circuit FIGURE 4 is a lumped constant representation ofintegrated circuits for: (a) receiving compression-modulated RF carrierpulses at a relatively low-power level from channel 33; (b) receivingphase control carrier pulses on channel 83; (c) shifting the phase ofthe phase control carrier in the phase shift unit 31; (d) modulating theRF pulses with the phase shifted pulses in the mixer 85; (e) amplifyingone of the modulation products in the power amplifier 30; (f) steppingup the frequency of the high power signal in the frequency multiplier86; (g) applying the final output pulses to an antenna 87; (h) detectingreturn signals to the antenna 87; (i) mixing the same in a mixer 88 atthe input of a preamplifier 89; and (j) passing the detected signalsfrom amplifier 89 through the phase shift unit 31 for delivery to anoutput channel 34.

For the purpose of the present example, the operation will be such thatthe RF pulses applied to channel 33 will be at a frequency of 2.125 gc.,:0625 mc., the swing of 1.25 me. being from low frequency to highfrequency by pulse compression generator control of the oscillator 41 asshown in FIGURE 3. The phase control carrier applied to terminal 83 willbe at 125 mc. The signal applied to the antenna 87 will be 9 gc. and theoutput signal on channel 34 will be at 500 mc. The module delivers onewatt peak power to the antenna 87 at 9 gc.

The compression-modulated RF carrier pulses applied to the channel 33pass through a tuned filter 100 at the input of the mixer 85. A secondtuned filter 101 is located in the output channel leading from the phaseshift unit 31 and is tuned to 125 me. for modulating the 2.125 gc.carrier pulse. The output circuit 102 is then tuned to the upper sideband or 2.250 gc. for driving the power amplifier 30. The phase shiftingunit 31 is employed to control the phase of the carrier at the outputtuned circuit 102.

Each of the plurality of modules 14 is adapted to be plugged into themanifold 40 so that the RF carrier pulses in a single channel in themanifold 40 are distributed to each of the channels 33, shown in FIGURE4, of each of the modules 14. The outputs at channel 34 of each of themodules are then summed in a single channel located in the manifold 40to provide a summed output at the channel 45. A single phase controlcarrier channel is located in the manifold and provides phase controlcarrier signals to each of the channels 83 while a plurality ofreference voltage input channels in the manifold 40 are respectivelyconnected to channels 35 of each module.

Phase shifting by line length switching Beam scanning is provided forthe antenna made up of a plurality of modules 14. As shown in FIGURE 4,beam scanning is produced by switching discrete lengths of transmissionline into the antenna feed system and more particularly into the channelthrough which the 125 mc. phase control carrier is transmitted. This isa steptype phase shifter. The size of the smallest step is important indetermining the complexity of the control circuit. In the unit 31, fivetransmission lines are employed and are of such length as to providephase delay units 111-115 of 11 /4, 22 /2, 45, and 180 delays,respectively, at a frequency of 500 mc. The 125 mc. signal applied toterminal 83 will undergo delays one-fourth of the amounts noted.

The phase shifter and switching unit 31 includes diodes and 121 formingan input switch. The common juncture between diodes 120 and 121 isconnected to diode swtches 122 and 123. Delay line 111 is connected todiode 123 and thence, by way of diode 124 and condenser 125, to theinput channel 126 leading to the second stage of the phase shifter 31.The diode 122 is connected by way of condenser 127 to channel 126. Theswitches 122, 123, and 124 are selectively biased under the control of abistable multivibrator 128. A second multivibrator 129 controlstransmission through, or the bypass channel for, the second delay line112. Multivibrators 130, 131, and 132 similarly control inclusion ordeletion of lines 113, 114, and 115, respectively, from the transmissionchannel for the mc. phase control carrier. A sixth multivibrator 133 isconnected to the output of multivibrator 132 and in turn feeds a TRswitch comprised of diodes 137 and 138.

The switch control line 140 leading to the multivibrator is suppliedfrom a clock input channel 141 at 1 mc. by way of an AND gate 142. Thesecond terminal of the AND gate is fed by voltage comparator unit 143.The line 144 of multivibrator 128 is connected by way of condenser 145to the input line 146 of multivibrator 129. Similarly, condensers 147-150 connect multivibrators 129-133 in a ripple-through configuration.From zero phase delay, the first clock pulse actuates multivibratorswitch unit 128 to include line 111 in the 125 me. circuit. The secondclock pulse actuates units 128 and 129 to remove line 111 and to includeline 112. The third pulse actuates unit 128 to include line 111 withline 112. The fourth pulse actuates units 128, 129, and 130 to removelines 111 and 112 and to include line 113. Thus, a digital progressionis employed in increasing the delay in the delay line unit.

The multivibrator 128 is coupled by way of lines 151 and 152 to adigital-to-analog converter 153. Similarly, all of the othermultivibrators are coupled to the digitalto-analog converter so that thestate of the switching networks is indicated by an analog signal on theoutput line 154. Switch unit 133, while introducing no delay, appliescurrent to converter 153 proportional to 360 phase delay so that theline switching sequence may continue through two cycles or 720. Theoutput signal from converter 153 is applied to the second input of thevoltage comparator 143.

In operation, a reference voltage representative of the desired phasedelay for module 14 is applied to the input terminal 35. So long as thereference voltage exceeds the output from the converter 153, the outputfrom the comparator 143 enables the AND gate 142. With the AND gate 142conductive, the clock pulses from. terminal 141 successively shiftconduction between the various flipfiops. When the output of theconverter 153 equals the reference voltage on channel 35, the AND gate142 discontinues transmission of the clock pulses and the desired delayis then fixed in the phase shift unit 31. Thereafter, the simultaneousapplication of the compressed RF carrier pulse and the phase controlcarrier pulse to terminals 33 and 83, respectively, will produce a pulseof 2.25 gc. at the output of the tuned circuit 102 in the mixer 85. Thephase of the 2.250 gc. signal at circuit 102 is equal to the phase delayin the unit 31.

The signal from mixer 85 is then applied to the power amplifier 30 fordelivery of about two watts peak power at 2.25 gc. to the input of thefrequency multiplier 86. The multiplier 86 consists of resonant circuitsin which a diode 160 is the active element. The multiplier is aquadrupler for delivery to the output channel 161 of a pulse whosefrequency is 9 gc. at a peak power level of about one watt. The latterpulse is applied by way of a TR switch diode 162 to the antenna 87 forradiation at the phase set by the phase delay unit 31.

Immediately after pulse transmission from the antenna, the controlmultivibrator 163 for the TR switch 162, 164 changes state so thatreturn signals detected by the antenna 87 pass through TR switch diode164 to the input to a mixer 88. The mixer 88 is supplied with an 8.5 gc.local oscillator signal on channel 165. The lower side band modulationproduct at 500 mc. is applied to the IF preamplifier 89. The lattersignal then passes through the switch diode 138 and the phase shift unit31 where the signal undergoes a delay of four times the delay of thephase control carrier. This is with the same delay unit setting asemployed during the transmit operation. The delay IF signal then passesthrough the output switch diode 121 to the output channel 34 leading tothe manifold. While not shown, control units for TR switch 120, 121 andTR switch 137, 138 will provide bias voltages therefor in the samemanner as the bias is supplied TR switch 162, 164.

More particularly, it will be recalled that the phase control carrierapplied to terminal 83 was at a frequency of 125 mc., and that it passedthrough the phase shift unit 31 to control the phase of the RF pulseapplied to the antenna 87. Since the multiplier 86 quadruples thefrequency, the phase shift introduced by the unit 31 is also quadrupledin the antenna drive signal as it appears on channel 161. Thus, with theoutput of the IF preamplifier 89 at 500 mc., the output signal onchannel 34 will have exactly the same phase shift as introduced into theantenna drive pulse. Thus, the same phase shift unit is used for boththe transmit and the receive cycle and the beam direction is the ,samefor receiving as for transmitting.

With power amplifier 30 present, module 14 includes its own powergeneration means and thus operates on low level signals from themanifold. The circuit 30 raises the power level by about 20 db in thepreamplifier section 30a, about 6 db in the driver 30b, and about 4 dbin the output section 300. By way of example, the power applied to theinput of the preamplifier would be about 2 milliwatts (mw.) peak or 0.2mw. average power. The signal at the input to the driver 3012 would beabout 200 mw. peak or 20 mw. average. The power applied to the outputstage would be about 800 mw. peak or 80 mw. average. The power outputfrom the output stage would be about 2 watts peak or 0.2 watts averagepower. In accordance with the construction hereinafter to be described,the multiplier would operate to increase the frequency from 2.25 gc. to9 gc. with an insertion loss of 3 db to provide one watt peak power tothe antenna 87. Thus, the power generation chain consists of 3 or 4amplifier stages at 2.25 gc. followed by an X4 varactor multiplier withan output at 9 gc.

Mixer In the system illustrated in FIGURE 4, as in other microwavesystems where a high-frequency, low-level return signal is employed, thequality of the receiver largely determines the other system parameters.For operations at frequencies transmitted by antenna element 87, thenoinse level of the mixer 88 presents the principal problem and themixer comprises a critical and principal component of the receiverportion of FIGURE 4.

Mixer 88 converts the received signal to a lower frequency preferablywith a minimum of added noise. To optimize the noise level for thereceiver, both the signalto-noise ratio of the mixer and the conversionloss in the mixer must be as low as possible. The detected signal fromdiode 164 and a local oscillator output signal on line 165 of FIGURE 4are applied to a semiconductor junction and the difference as IF outputsignal is extracted.

For operation at frequencies in the X-band, the mixers illustrated inFIGURES 5-12 may be employed. Operation thereof is characterized by lowloss, employing high ratio couplers of integrated circuit form.

More particularly, as shown in FIGURE 5, a semiconductor Wafer 210 isprovided with a signal input strip 211 and a local oscillator inputstrip 212. Strips 211 and 212 are metalized regions overlaying a highresistivity semiconductor wafer. The metalized regions 211 and 212 leadto the input portions of a hybrid coupler 213. The coupler 213 isprovided with parallel sections 214 and 215 which are about one-quarterwavelength long and are of a width substantially greater than the widthof the strips 211 and 212. Two shunt strips 216 and 217 are spacedapproximately one-quarter wavelength apart and extend between sections214 and 215. Output lines 218 and 219 extend from the coupler 213.

A pair of quarter-wave transformer sections 220 and 221 extend from theoutput strips 218 and 219, respectively, and make contact with terminalsof surface-oriented diodes 222 and 223, respectively. Output conductors224 and 225 lead from the other terminals of diodes 222 and 223 tooutput capacitors 226 and 227 to provide an output signal at outputterminals 228 and 229.

With strip-line transmission lines overlaying the semiconductor wafer210 and With surface-oriented diodes of a construction hereinafterdescribed, a signal in the X- -band may be converted to IF with about a5 db loss. For example, a 9 gc. signal may be applied to strip 211. Alocal oscillator signal at 8.5 gc. may be applied to the input strip212. As a result, an IF signal of 500 mc. is produced at terminals 228and 229.

The surface-oriented diode 222 is illustrated in one form in FIGURE 6.The wafer 210, of intrinsic silicon, is provided with a ground planeconductive layer 230. The intrinsic silicon forms a high resistivityzone above the ground plane layer 230. An N-type alloyed region 231 anda P-type alloyed region 232 are formed in the surface of the wafer 210opposite the ground plane layer 230. A silicon dioxide insulating layer233 is formed over the upper surface of wafer 210 to cover the surfaceemergence of the junctions forming the boundaries between the P- typeand N-type alloyed sections and the intrinsic wafer 210. An N-type metalalloy strip 220 is then formed on the surface of the wafer 210 so as tomake electrical contact with the N-type region 231. A P-type metal alloystrip 224 is formed on the surface to make electrical contact with theP-type region 232. The P-type and N-type metal alloy strips 220 and 224are evaporated onto the surface through holes in oxide masks defined byphotolithographic techniques. The metal alloy strips are then alloyedinto the silicon to produce the N+ and P+ regions between the strips andthe N-type and P-type regions 231 and 232. An intrinsic region 234 isdisposed between the N and P regions, the boundary junctions of whichare shown in dotted outline.

Such fabrication of the surface-oriented mixer diode is in a formcompatible with the integrated circuit construction. The diode is asubstantial improvement over conventional microwave mixer elements.Previous mixer diodes have been of the point contact variety in order tomaintain low junction capacitance. The present construction has achievedjunction capacitances of 0.05 picofarads (pf.) or less. When biased byrectification of the local oscillator signal to obtain the best noisefigure, the shunt resistance of the junction of the present invention isapproximately 400 ohms. In ordinary mixer diode configuration, thisvalue of resistance is transformed to an input impedance of about 50 to100 ohms by the package inductance and the junction capacitance. In thepresent case, the junction diameter of the diode is approximately 0.1mil (0.0001 inch). Production of a semiconductor junction of this size,as above noted, employs intrinsic silicon having side-by-side alloyzones to form confronting edge junctions that will give the surfacediode effect.

The material required for the integrated circuit preferably will providea suitable substrate for microwave strip transmission lines and forforming the mixer semiconductor junctions. Intrinsic silicon and highresistivity gallium arsenide may be employed for mixer diodes, whereasgermanium has characteristics which are not suitable for both themicrowave strip transmission line and the diode construction. Whereextremely low loss transmission lines are required, low loss dielectricswith deposited silver conductors are employed. Yttrium-irongarnet (yig)substrates may also be employed for this purpose.

FIGURE 7 illustrates a modified form of surface-oriented diode whereinside-by-side diffusions of oppositeconductivity type impurities areformed on the upper surface of an intrinsic silicon wafer 240. TheN-type diffused zone 241a and the P-type diffused zone 242a arecharacterized by an edge junction that will give the surface diodeeffect. The zones 241a and 242a are formed partially in N+ and P+diffusion zones 241 and 242, respectively, which in turn are formed inan insulated island of intrinsic silicon about 1 mil wide and 5 milslong formed in the wafer by an insulating layer 243 of silicon dioxide.

The spacing between the edges of the diffused N+ and P+ zones 241 and242 is about 0.3 mil in zone 247. However, the zone 248 between theconfronting junctions of the N and P zones 241a and 242a is about 0.1mil wide. The capacitance of the junction is defined by the effectivejunction area of the shallow diffusions and the reverse breakdown by theshallow diffused spacing and the intrinsic or I-layer concentration.Conductivity modulation under forward current conditions is minimized byreason of the effective increase injection area of the anode of the deepP+ diffusion. The problem is in defining the I-layer between thediffusion fronts so that a sufficient current density can be obtained atreasonable current levels. For currents of 20 milliamps, about a 4square mil area will give a current density of 200 amps per squarecentimeter required for conductivity modulation. An insulating layer 244covers the surface of the wafer except for metalized contact zones 245and 246.

Surface-oriented diodes of the type illustrated in FIG- URES 6 and 7 maybe employed in the mixer of FIG- URE 5. Where additionalcurrent-carrying capacity is required of surface-oriented diodes, as inthe transmitreceive switches employed in various systems, theconstruction such as shown in FIGURE 8 may be employed.

In FIGURE 8, the transmission lines 220 and 224 are shown contacting thediffused zones 241 and 242, respectively. The diffused zone 241 hasthree fingers. The zone 242 has two fingers with the fingers beingenmeshed or interdigitated to provide a junction of highcurrent-carrying capability. Such a construction exhibits low junctioncapacitance under moderate reversed-bias conditions and low loss.

Intrinsic silicon as the substrate material for the diodes providesinsulation isolation for any number of components deposited upon it andalso provides a low loss structure. The structure is readily adaptableto receiving strip transmission lines deposited directly onto thesilicon. In accordance with one mode of fabrication, a ground planeconductor is evaporated onto the bottom of an intrinsic siliconsubstrate of approximately 5 mils thickness.

Silicon dioxide on the top is etched to expose the silicon wheretransmission lines are required. Gold is then evaporated over the entiresurface and selectively removed to leave gold over the exposed regionsof the silicon. Preferably, in order to maintain the propagationproperties of the lines, the alloying of gold with silicon will beavoided, as by the forming of a thin layer, a few microns thick, of amaterial such as molybdenum between the gold strips and the silicon.

As an alternative mode of fabrication, a hot substrate evaporation ofgold onto the intrinsic silicon is carried out. The gold is then etchedaway to leave he transmission lines where required. At microwavefrequencies, the degradation of leakage current due to the introductionof the gold into the silicon is of little consequence. In the samemanner, aluminum strip transmission lines may be formed on galliumarsenide to form the transmission line pattern on a given substrate.Thus, the mixer of FIGURE 2 is a flat, integrated circuit package. Theintegrated circuit may be part of more complex circuits formed on thesame or interconnected substrates.

Referring again to FIGURE 7, a diffused, surfaceoriented diode withinsulation isolation represents a preferred embodiment of the invention.One procedure for forming this structure is shown in FIGURES 9-11. Thestructure illustrated in FIGURES 9-11 is similar to the structureillustrated in FIGURE 7, and corresponding parts will therefore bedesignated by corresponding reference numerals. However, the structureof FIGURES 9-11 is illustrated as round, while the structure of FIGURE 7is rectangular. The surface of a single crystal, highresistivitysubstrate of N-type material is etched on the surface to form a mesa240a on the top surface. The oxide layer 243 is then grown over theupper surface of the etched wafer and over the mesa 240a to form aninsulating layer over the entire etched surface. The material formingthe bulk substrate 210 of the structure in FIG- URE 7 is then depositedor grown over the top of the slice 240 to completely cover theinsulation layer 243 and to surround the insulation covered mesa. Afterthe bulk material 210 is grown onto the top of the wafer, the top (inFIGURE 9) of the bulk material 210 is lapped smooth for receiving theground plane conducting layer 230 shown in FIGURE 7.

The substrate 240 is then lapped so that all of the original wafer isremoved except for the mesa which is then the island 240a located in awell or depression surrounded by the isolation layer of silicon oxide243 as shown in FIGURE 10. Thereafter as shown in FIGURE 11, through aphotomasking technique, N+ and P+ diffusions are made to form the zones241 and 242 of opposite-conductivity types in the island 240a. Insidethe island there is then high enough impurity concentration for good lowresistivity ohmic contact. The low resistivity (high concentration)diffusions have a very narrow intrinsic zone between them, of the orderof 0.3 mil wide. Into this area of original material, there are made twovery shallow diffusions 241a and 242a of N and P-type materials,respectively. The diffusions are very shallow (3 lines or 3 x 0.016 mil)with high concentrations. The junction between the N and P shallowdiffusion zones 241a and 242a is not or need not be accuratelypositioned as long as it is within the 0.3 mil strip. The junctionbetween the two zones is 1 mil wide and 3 lines deep or an area of 1 x 3x 0.016 mil=0.048 sq. mil. This results in a very low capacitancejunction suitable for use in the mixer of FIGURE 5. Contacts are readilyapplied to the two N+ and P-lregions of FIGURES 10 and 11 to be used forbonding or pressure contacts alloyed in.

Where the diode is to be employed in the mixer applicatron, theseparation 248, FIGURE 7, between the junctions will be reduced to zero.The boundaries of the two zones will thus be contiguous.Surface-oriented diodes for use 1n switching applications will beconstructed with separat on between the two zones and for high currentcapability, will be interdigitated as shown in FIGURE 8.

1 1 In FIGURE 7, transmission lines 245 and 246 extend along the top ofthe insulating layer 244 to contact with the zones 241 and 242respectively. Preferably, the transmission line leading to and from thesurface-oriented diode, expect for the insulation over the junctions asshown in FIGURE 7, will be formed directly on the surface of thesemiconductor material 210. Preferably, ground plane conductor 230 andthe low resistance conductive strips 245 and 246 are gold and overlay anextremely thin film of a metal such as molybdenum, as above noted, or ofvanadium, platinum, nickel or tungsten evaporated to a thickness of afew microns to form an underlayer for each strip. The underlayer havinga high eutectic temperature will prevent the formation of lossy zonesthat would otherwise be present where gold strips to be formed directlyonto the silicon surface and then subjected to treatment at temperatureswherein th silicon would become intermixed with the gold at the boundarythereof. The ground plane layer 230 is shown as having been formed oversuch an underlayer 249 on the bottom surface of the structure as shownin FIGURE 7.

Thus, for switching'use, the diode junctions are spaced apart to form aPIN diode junction. For mixer use, the confronting portions of thejunctions are contiguous or overlap to form a PN diode junction. In thelatter case, the boundary of the last diffused zone would define thediode junction.

In FIGURES 611, surface-oriented diodes are formed in a semiconductorsubstrate and thus involve a single basic building material. In FIGURE12, a modified form of mixer construction has been illustrated. In thisembodiment, a relatively thick high dielectric ceramic layer 251 has aground plane conductive layer 252 on the bottom face thereof with a thinhigh eutectic metallic layer 252a thereunder. The strip-line conductors253 and 254 are formed on the upper face of the ceramic substrate 251. Asurface-oriented diode 255 having diffused P and N-type zones 256 and257 respectively formed therein is then employed in a sandwichconstruction to form a diode which corresponds with the diode 222 ofFIGURE 5. The diode 255 is formed in a thin Wafer or chip ofsemiconductor material and then placed face down onto the ends of thestrip-line conductors 253 and 254. An isolated insulation layer 259 isthen formed over the top of the ceramic substrate 251 to encompass thediode 255. A glass evaporate layer 258 is then deposited on top of theinsulated layer 259. A high eutectic metal layer with a ground planesurface conductive layer 260 is then formed on top of the layer 258. Aconductor serves to connect the ground plane layers 252 and 260 togetherfor forming a shielded sandwich construction for the mixer transmissionline elements and the surfaceoriented diode.

Frequency multiplier The frequency multiplier 86 of FIGURE 4 has beenfurther illustrated in a lumped constant equivalent form in FIGURE 13.The L matching section includes a series inductance 310 and a shuntcapacitance 311. A low pass filter comprised of series inductances 312and 313 and shunt capacitance 314 provides a low pass filter tuned to2.25 gc. The resonant circuit which includes the active element iscomprised of series inductances 315 and 316. A shunt capacitance 317 isconnected to the juncture between inductances 313 and 315. A seriesresonant shunt circuit comprised of inductance 318 and capacitance 319is connected to the juncture between inductances 315 and 316. A shuntcircuit comprised of an inductance 320 and a diode 160 is connected tothe juncture between inductance 316 and the series inductance 322forming a part of the output band pass filter. The band pass filterincludes series inductance 322, capacitance 323, capacitance 324, andseries inductance 325. Shunt capacitance 326 is connected to thejuncture between capacitances 323 and 12 324. The output L matchingsection includes series inductance 327 and a shunt capacitance 328.

The formation of the multiplier in one integrated circuit configurationis shown in FIGURES 14 and 15. Prior art systems generally are limitedas to power level at frequencies such as encountered in the X-bandbecause of the small geometry necessary for operation. For example, over25 watts power output is available from a single transistor atfrequencies as high as mc. For amplifiers utilizing one transistor perstage at 1000 mc., about 200 milliwatts are available and at 3000 mc.,this is reduced to about 10 milliwatts. The large power capabilities atlower frequencies and efficient frequency multiplication are combined inthe system shown in FIG- URES 14 and 15 to obtain the necessary power athigh frequencies. By this means, peak power output capability ofintegrated microwave sources of about 1 watt can be obtained atfrequencies well above 8 gc.

The multiplier shown in FIGURES 14 and 15 employs a varactor diodeoperating as a quadrupler with idlers at second and third harmonics.More particularly, thhe tuned circuit 318 and 319 may be considered tobe resonant at the second harmonic and the tuned circuit 320 and 160 atthe third harmonic. Because of integrated circuit construction, ratherthan lumped constant construction, there is contribution to the severalresonance conditions from most or all of the elements in the unit sinceisolation of any one element is not possible as in lumped constantcircuit construction. Therefore the description as to resonant circuitsis in terms of result with a construction shown in FIGURE 14. Thecircuit will change the frequency from an input frequency of 2.25 gc. toan output frequency of 9 gc.

As shown in FIGURES 14 and 15, the varactor diode and the strip-linetransmission circuits forming inductance and capacitance are formed on asemiconductor substrate. The substrate 330 has about one-half of itsarea covered by a highly conductive surface layer 329. The layer 329 isthen covered by a thin dielectric layer 339 so that layer 329 serves asa common plate for all but two condensers in the multiplier.

The input L section is formed by the strip transmission line 310 whichextends over the thick dielectric portion of the substrate 330 to theplate 311 of the input capacitor. The capacitor 311 overlays therelatively thin dielectric layer 339 to form a condenser with the commonconductive layer 329. The loop 312 forms an inductance over the thickdielectric layer and leads to a capacitor plate 314 over the thindielectric layer. Similarly the loop 313 leads to the capacitor plate317. The transmission line filter system will thus be characterized bylong thin transmission lines over thick dielectric sections to provideprimarily inductance characteristics. Wide transmission line sectionsoverlying thin high dielectric layers form zones in the transmissionline system primarily capacitive in nature. The loop 315 extends fromplate 317 over the thick dielectric to the juncture with a loop 318which leads to a capacitor plate 319. Loop 315 also leads to oneterminal of the varactor diode 321. A strip extending from the juncture320 and loop 322 then leads to a capacitor plate 323. The capacitorplate 323 is positioned on top of a conductive layer 340 which overlaysone-half of the condenser plate 326. Condenser plate 324 similarlyoverlays the plate 326. The transmission line loop 325 then extends tothe output capacitance plate 328 with the matching inductance 327extending from the plate 328. The plate 326 is capacitively coupled tothe capacitor plates 323 and 324 and to the high conductive layer 329.

For frequencies within the range of from 0.5 to 5 gc., input and outputimpedance will be on the order of from 10 to 50 ohms. Capacitance valueswill be within the range of from 5 to 75 picofarads (pf.) (10 farads)and inductances between 0.5 and 10 nanohenries (nh.) (10 henries).

Since relatively high Q capacitances are necessary for operation of themultiplier circuit, an extremely thin, high dielectric constant layer339 is employed. The inductances have low loss and high effectiveinductance per unit length. Thus, in the planar construction of FIG-URES 14 and 15 large spacing between thin conductive loops on the uppersurface of the slice 330 and the ground plane conductor forminductances. In addition, the wide conductive layers 339 and 340 over athin high dielectric layer form capacitances. Preferably the sub strate330 will have a dielectric constant of the order of from 4 to 12 and athickness of from 0.005 to 0.010 inches. The layers 339 and 340 willhave a dielectric constant of about 40 to 50 and a thickness of 0.000 1inch.

The filters at the input and output of the multiplier form traps toprevent power flow from the multiplier other than at the desiredfrequency. At the same time, the dissipation of power in the varactor isheld at a minimum while maintaining the necessary band width of themultiplier. A significant band width is required due to both thecharacteristics inherent in the operation of the non-linear reactance ordiode 160, and the undesired variations in temperature of thesemiconductor junction capacitance. The multiplier band width must besufficient to allow buildup of voltage amplitude across the diodejunction, and thus develop bias voltage to bring the multiplier intoproper operating range.

The dielectric requirements for both the capacitors and inductors thusmay be fulfilled on the common substrate or slice 330. Diode fabricationtechniques indicated in FIGURE 16 may be followed.

In step (a), N-type material is epitaxially deposited onto an N+ galliumarsenide slice. After the slice is polished, a thin film of silicondioxide is reactively sputtered onto the surface to a thickness ofapproximately 6000 angstroms. The wafer 330 with the N-type epitaxiallayer 331 and the silicon dioxide surface layer 332 are shown in step(a).

By a photomasking technique, a hole 333 is then cut in the layer 332 asshown in step (b). The slice is then sealed in a quartz ampoule withZnAs and is diffused for about two minutes at 900 C. The result is shownin step (c) with the diffusion of zinc 334 through the hole 333 beingaccomplished. The depth of the diffusion is of the order of about 0.3mils. In addition to the diffusion through the hole 333, the zinc alsodilfuses through the layer 332 to form a thin P layer under the oxide.The oxide layer is then removed as shown in step (d). As shown in step(e), the slice is treated with a sulphuric acid etch to remove the thinP layer outside the regions defined by the hole 333. At this point, anew oxide layer 335 is sputtered onto the slice as indicated in step(f). By photomasking and selectively etching, the oxide layer 335 isremoved over the zone occupied by the zinc diffusion 334, as indicatedin step (g). A transmission line strip is then evaporated onto the sliceand alloyed with the gallium arsenide to form the contact 336, as shownin step (h).

After the formation of the varactor junction, the upper half of theWafer 330 is masked and a conductor is alloyed to the lower unmaskedportion to form layer 329. The masking is then removed and a 1 mil thickdielectric is deposited to form layer 339. Upon this substrate,conductors shown in FIGURE 14 are incorporated by photolithographicmasking techniques. Gallium arsenide and intrinsic silicon are preferredas substrate materials. A yttrium-iron-garnet substrate may be employedfor the multiplier network. Gold may 'be employed on silicon andaluminum on gallium arsenide as the conductive materials.

While a planar construction is shown in FIGURE 15, it will he recognizedthat other modes of fabrication may be employed for providing themultiplier network on the semiconductor substrate. In FIGURE 17 amesatype construction is shown in which a mesa is first formed on thesubstrate 330 to provide a site for the diode 160. An insulating layer330a is then formed on the surface of the substrate 330 extending upalong the slopes of the mesa for insulating the junction therein.

Thereafter, the conductive layer 329 will be formed over a portion ofthe surface of the substrate for forming the common plate for condensers311, 314, 317, 319, 326 and 328. The thin layer 339 of high dielectricmaterial is then formed over the conductive layer 329. Thereafter, thecondenser plates and the strip line loops will be incorporated in thecircuit configuration shown in FIGURE 14.

The parameters in the construction illustrated in FIGURES 14-17, ingeneral, are distributed constants. Resonances will be present withinthe system, such as illustrated in the graph shown in FIGURE 18.Reactances in the resonant circuits are plotted as a function offrequency. The impedance of the circuit, as viewed from the terminals ofthe varactor 160, is illustrated by the dotted lines 350. The reactanceof the varactor diode is plotted as the solid curve 351.. The dottedcurve 352 is the reciprocal of curve 351.

The circuit construction of FIGURE 14, as further detailed in FIGURES15-17, operates such that the intersection of the reciprocal curve 352and the reactance curve 351 occurs at the input frequency of 2.25 go.and at the harmonic frequencies of 4.50,. 6.75 and 9.0 gc.,respectively.

While FIGURE 1 illustrates an array of integrated circuits in theantenna module 14, one form of construction of the phase shift delayline is shown in FIGURE 19. The delay line plate 360 has threeintegrated circuit modules 361, 362, and 363 mounted thereon. Such aWafer may be included in the package shown in FIG- URE 2.

The first module 361 may include the switches SW1 and SW2 of FIGURE 4.The module 362 will include the switches SW3 and SW4 and the module 363will include switches SW5 and SW6. The delay lines 111-115 are formed onthe plate 360 with the line length being progressively longer as byfactors of 2, from one line to another. Plate 360 is provided with inputtransmission line terminals on the tab 365 for transmission to and fromthe plate 360 of the phase control carrier and the received signalvoltages as well as the clock pulses.

With integrated circuits 361363 of form illustrated, the wafer 360 maybe relatively small with maximum dimensions of the order of about aninch.

FIGURE 20 is illustrative of the construction of the integrated circuitwafer for the switching networks. The substrate 370 is ofpolycrystalline silicon. Insulation isolation cups 371, 372, and 373surround and isolate islands 374, 375, and 376 of N-type material. Thesurfaceoriented diode formed in the island 374 may be of the typeillustrated in FIGURE 7 and will serve as either the transmit diode 122or the receive diode 123 of FIG- URE 4. A diffused N+ zone 377 isconnected to a strip conductor 378 which is formed over a surfaceinsulation layer 379. A diffused P+ zone 380 is then connected byconductor 381 to the emitter terminal of transistor 382.

A transistor 382 is formed of the N zone 375, P zone 383, and N+collector zone 384. A conductor 385 connects the collector of thetransistor 382 to a resistor 386, the resistor being formed by a P-typedifiusion zone 387 in the N-type island 376. Lead 388 is connected tothe resistor 386 and extends to other circuit elements.

With construction of the type illustrated in FIGURES 19 and 20, thephase shift delay lines and the control networks in integrated circuitform may be included in module 14. At some frequencies and for someapplications, it will be desirable to construct phase shift modulesseparate from the radiation module 14. Such phase shift modules may beformed as shown in FIGURE 19 and would be connected in the antennacircuit between the manifold 40 and the radiation module 14.

IF preamplifier The IF preamplifier of FIGURE 4 is of integrated circuitconstruction and has a gain of about 50 db. Such high-gain integratedcircuit amplifiers operating at frequencies in the range from 200 me. tothe low gc.s, are subject to oscillation as a result ofelectromagneticallycoupled feedback Within the integrated circuitpackage. This is primarily due to the very close spacing between theactive and passive components formed integral with the semiconductorsubstrate.

FIGURE 21 illustrates an integrated circuit 410 of construction suitablefor the IF amplifier 89 of FIGURE 4. The circuit 410 is comprised of asubstrate 412 of single crystal, high resistivity silicon or othersemi-insulating or high-resistance semiconductor material having firstand second surfaces 414 and 416. The resistance required between thesurfaces 414 and 416 will vary with the frequency at which the circuitis operated, the lower the frequency the greater the resistancerequired. However, for higher frequency applications, high resistivitysemiconductor material is adequate. The components for the IF amplifierare formed at the surface of the semiconductor substrate 412 using anyconventional technique. For example, a transistor 418 may be formed inthe surface by sequentially diffusing N-type, P-type and N- type regionsinto the surface 416 of the substrate through openings etched in anoxide film 420. Alternatively the components may be formed on thesurface of the substrate by epitaxial techniques. The circuit may alsoinclude interconnecting strip conductors such as 422, 423 and 424 whichmay be placed directly on the high resistivity substrate 412 or on theoxide film 420. The conductors may also form inductors such as indicatedby the dotted outline at 426.

An insulating layer 428 is deposited over and adherently bonded to theportion of the second surface of the substrate 412 which is exposed andto the components of the circuit and is therefore integral with thesubstrate. Metalized films 432 and 434 are adherently bonded to theinsulating layer 428 and to the first side 414 of the substrate. Whenthe metalized films 432 and 434 are connected to ground, as representedby the conductors 436 and 438, the entire integrated circuit is disposedbetween two closely-spaced ground planes. As a result of the closelyspaced ground planes, the electromagnetic radiation from any particularcomponent is attenuated by a loss factor of Loss db wherein k isdependent upon the dielectric constant of the material between thecomponents and the respective ground planes, d is the distance from thepoint at which the electromagnetic wave is generated, and s is thespacing between the ground planes. Although the attenuation increases asthe spacing between the ground plane decreases, the insulating layer 428should be at least 1.0 mil thick and is preferably from 35 mils inthickness. It will be desirable toenvelope the entire circuit structure,including the substrate and insulating layer, in the metalized groundplane.

In FIGURE 21 the insulating layer 428 is glass. The glass is selected soas to have a coefficient of thermal expansion closely matching that ofthe substrate so as to provide thermal-mechanical stability. Further,for stabilizing the high-frequency transmission lines, the insulatinglayer 428 is preferably about the same thickness as the substrate 412 sothat the dielectric constant between the circuit components and each ofthe ground planes will be approximately equal. However, the insulatinglayer 428 may be any material which may be adherently bonded to thesubstrate 412, which is chemically compatible with the substrate andactive components at various temperatures, and which has a thermalcoefiicient of expansion compatible with that of the substrate 412 sothat the substrate will not be placed under stress due to temperaturechanges, and may be of any desired thickness, usually thin for amplifierapplication and relatively thick for transmission line application. Thedielectric constant may be very closely matched by making the insulatinglayer 428 from high-resistivity semiconductor material of the same typeas the substrate 412. This can be accomplished by epitaxial growth, if asingle crystal is desired for part of an active component, or by anotherprocess where a polycrystalline structure will sufilce. The substrate412 should be relatively thin, for amplifier applications where it isdesired to place the ground planes as close to the active components aspractical, and will usually be less than about ten mils in thickness.

As an alternate structure, the substrate 412 may be a dopedsemiconductor material rather than intrinsic silicon or semi-insulatingsemiconductor material. In such case an insulating layer is providedbetween the metalized film 434 and the substrate so that the groundplane formed by the film 434 will be electrically insulated from thecomponents of the circuit. Such an insulating layer may be any suitablematerial such as silicon dioxide, aluminum trioxide, glass, or the like,but is preferably glass. The device 410 is particularly suited for lowerfrequency applications where the dielectric constant should be higher.

An IF amplifier or the like is fabricated on and in the surface of thesubstrate 412 using any conventional technique as heretofore described.Then the glass insulating layer 428 is formed by applying a liquid inwhich a high concentration of very fine glass particles is suspended.The glass particles are allowed to settle from the liquid and deposit asa sediment on the surface of the substrate and over the components ofthe circuit. The sedimentation process tends to uniformly deposit theglass particles over the components of the circuit and produce anessentially planar surface. Then the substrate is heated to atemperature sufiiciently high to fuse the glass particles into a solidmass which adherently bonds to the exposed portion of the substrate; theoxide insulating film 420, if any, or the components of the circuit, asthe case may be.

Although the insulating layer 428 was identified as glass applied bymeans of the liquid suspension technique, the insulating layer 428 mayalso be formed from glass or quartz which is evaporated in a high vacuumand condensed on the surface of the substrate. The metallized films 432and 434 may then be deposited by a conventional evaporation andcondensation process.

The exposed surfaces of the substrate and insulating films are thenmetalized, preferably by evaporating and condensing a metal onto thesurfaces, or by other wellknown techniques. Gold, aluminum or othersuitable metal may be used for this purpose. However, if gold is to bedeposited directly on a silicon substrate, a thin layer, a few angstromsthick, of molybdenum or other metal which does not dope the silicon ispreferably deposited on the surface 414 before the gold is deposited toprevent doping of the silicon by the gold.

The integrated amplifier circuit is disposed between a pair ofclosely-spaced ground planes. The ground planes and the circuit areinterconnected so as to provide a rugged, sealed package. For highfrequency transmission lines, the dielectric properties between thecircuit compoponents and each of the ground planes may be madeapproximately equal for improved performance.

Beam steering reference voltage generatiom The present invention isdirected to a control system for generating families of referencevoltages such as the voltage applied to terminal 35, FIGURE 4, in eachmodule.

Where the antenna is made up of an array of elements arranged in rowsand columns as shown in FIGURE 23, each of the rows and columns may benumbered for convenience according to their position in the array. Toshift the beam of the antenna in a horizontal direction through an angleFIGURE 22, the phase of the RF energy applied to the radiation structurein each module in each column must be shifted by an amount which isproportional to the angle (p, the angle that the beam is to be shiftedfrom a line perpendicular from the face of the antenna, The phase shiftfor each module must also be dependent upon the location of the modulein the array. FIGURE 22 shows a top view of the antenna unit 12 and aplot of the phase shift versus distance from the center of the antenna.

As shown in FIGURE 23, the control unit 510 generates a referencevoltage which shifts the plase for the column n at the left edge ofantenna 12 through the same phase angle. As represented by the tappedresistor 510a in unit 510, the voltages applied by way of sample andhold units 510x to the columns of the antenna. Sample and hold units550x apply voltages to the row of antenna modules. Voltages are appliedto the columns in the right antenna half are the same for each columnbut are graded from a maximum at the edge column to near zero at thecenter column. The left antenna half columns similarly are controlled byreference voltages such as might be derived from resistor 5131). Theunit 550 similarly serves to control the vertical scan or beam position.To point the beam in a direction involving both the horizontal andvertical deflection, the reference voltage for a given antenna elementis the sum of the voltage required for the column in which a givenelement is positioned and the voltage required for the row in which thegiven element is located. Thus, as illlustrated in FIGURE 22, the columnat the left side of the antenna unit 12 would be delayed by an angle Thecolumn at the right edge of the antenna unit 12 would be delayed by anangle of Where the antenna array is one wavelength wide and where thedifference between the angle and is 360, the antenna radiation primarilywill be at 45 to the face of the antenna. In practice, however, theantenna generally is made many wavelengths wide as well as high so thatnarrow beams may be produced. When this is done, it is necessary toproduce phase shifts across the face of the antenna which are equal to N360. The factor N may be any integral number with practical valuesranging as high as to or more for phase shifts of around 5000 across theantenna.

In FIGURE 24 the controller for generating the horizontal and verticalreference voltages above noted is shown, with the controller forproducing the horizontal reference voltages being shown in detail.

In order to point the beam in a given direction, a binary number,proportional to the phase shift required for the edge column n, FIGURE22, is read into an input register 511 of unit 510 from a control source5100. The register 511 is connected to a switch unit 512. A referencevoltage is applied to the switch 512 by Way of input channel 513. Thedigital-to-analog converter of FIGURE 24, may in clude switch unit 512which, may be the same as in FIG- URE 4 which shows the construction onthe switch units SWl-SW6 and the connections to the ladder network. Theregister 511 may be composed of flip-flops as shown in FIGURE 4 or maycomprise other binary storage elements. These elements control switchesin unit 512 which in turn control the binary weighted resistance ladderof the type commonly used in digital-to-analog converters. Typical ofthe construction is the resistance network illusstrated in the unit 514.The resistance values are chosen so that the voltage at the output is /2k the value of the reference voltage on terminal 513 and k is the numberof switches in the ladder. When switch S2 is closed to the referencevoltage and all the other switches are connected to ground, the outputvoltage is /2k1 times the reference voltage, etc. This assumes that theseries resistances 514a are not present. Resistances 514a, however, areincluded for the purpose which will later be explained, In

operation the switch for each given ladder position is connected to thereference voltage if the bit in the corresponding register is 1, and toground if the bit is 0.

Theoutput of the ladder network 514 is applied by way of conductor 515to a second digital-to-analog unit including switch unit 516 whichcontrols a ladder network 517 and which is turn in controlled by acounter 518. A second counter 519 counts in parallel with counter 518. Adecoding logic network 520 is connected to counter 51?. Counters 518 and519 are controlled by a clock 521 which is connected thereto by Way ofan AND gate 522 and line 527. A control multivibrator 523 controls oneinput of the AND gate 522. The decoding logic network 520 has outputlines i to n with output lines n being connected by way of line 524 tothe reset terminal of the multivibrator 523.

A starting unit 525 is connected to the start terminal of themultivibrator 523. The starting unit 525 is also connected to the resetterminal of counter 519 and, by way of and OR gate 526, to the resetterminal of the counter 518.

One control terminal of the OR gate 526 is connected to the output of acomparator 533 which is connected at one input to the output line 529 ofthe ladder network 517 and at the other input to a comparison referencevoltage source 539. The comparator 533 produces an output signalwhenever the reference voltage 530 is less than the voltage on line 529.

The line 529 is also connected to a bus 531 at the input of a pluralityof sample-and-hold units 532i-532n. Line .5129 is connected by way of aninverting unit 540 to a bus 541 to sample-and-hold units 542i-542n.

The voltages appearing at the outputs of the sample and-hold units532i532n and 542i-542n are the voltages necessary to shift the beam fromantenna unit 12 through a horizontal angle represented by the referencevoltage from the numerical input unit 5100.

In a similar manner, a vertical control voltage generator 550 providesoutput voltages to sample-and-hold units 552i-552n and 562i562n forshifting the beam from the antenna unit 12 through a vertical anglerepresentative of the magnitude of the reference voltage applied fromthe reference numerical input voltage source 5500, The voltages from thesampleand-hold units may then be combined for application to thereference input terminals of each module (terminal 35 of FIGURE 4), sothat each module in the antenna unit will be adjusted to shift the phaseof the RF antenna excitation pulse in dependence upon the sum of thevertical and horizontal beam angles represented by the voltage on units5100 and 5500. The voltages may be combined from the sample-and-holdunits in the manner known in the art, and such as described inIntroduction to Radar Systems, Skolnik, McGraw-Hill (1962), p. 312 etseq.

In operation, where a scanning sequence of the antenna is desired, thenumbers to be read into the units 510 and 550 from the control sources510a and 550s come from the sequence generators or programmers. Theunits 510c and 550a may comprise part of a computer if the antenna is tobe pointed at some target, as would be the case in a target trackingoperation. In either case the voltage output on line 529 will then beproportional to the phase shift desired in the extreme or edge columnsof the antenna.

As soon as the phase shift number or signal has been read into the unit510, a start pulse is applied to the control flip-flop 523. This pulsealso resets the counters 518 and 519. As soon as the control unit 523 isset, the AND gate 522 changes state to allow the clock pulse train topass to. the counters 518 and 519. This causes the two counters toadvance together. The counter 518 controls the units 516 and 517, withthe reference input voltage being the voltage on line 515. As the countin the counter 518 increases, the voltage on line 529 increases inuniform steps.

In the explanation of operation of the reference generator whichfollows, it will first be assumed that the total phase shift across theface of the antenna is to be less than 360 Thereafter, operation for aphase shift greater than 360 will be explained.

For a phase shift less than 360, counter 519 will count in synchronismwith counter 518. The state of counter 519 is decoded to provide itindications on 11 individual output lines 520i-520n. The output voltageon line 529 for each step of counters 518 and 519 is a voltageproportional to the phase shift for each column, That is to say, thefirst stage of counters 518 and 519 results in a voltage proportional tothe phase shift for columns +1 and i of FIG- URE 23. The second stage ofcounters 518 and 51% results in avoltage for columns +ii and ii, and soon. It will be noted from FIGURE 22 that the phase required for column nis the negative of the phase required for column -n.

Counters 518 and 519 initially are reset to a state of all Zeros. Thisresults in a ladder output voltage on line 529 of zero volts for thefirst state of the counters. If the number of columns in the antenna isan even number, as shown in FIGURES l and 23, a reference of zero voltswould result in the phase shift introduced in columns i and -i alwaysbeing zero. This would induce a slight discontinuity in the phase slopeacross the antenna. To prevent this, the ladder network 514 is providedwith resistors 514a. These resistors offset the output of the ladder 514by an amount equal to one-half step of the output voltage.

The lines 520i520n, connected to the sample-and-hold units 532i-532n,are sequentially energized to cause storage of a sample voltage in eachof the units as the states of the output lines leading from decoder 520change. Similarly, the other half of the antenna is provided withreference voltages from bus 541 by way of inverter unit 540.

When the output on line 529 equals the reference voltage from source530, as applied to the comparator 533, the counter 518 is reset. Decoder520 serves to reset flipfiop 523 at the end of a phase control sequencethus inhibiting clock pulses to counter 519. Counter 519 is reset by thenext start pulse. The voltage from reference source 530 is set at avalue corresponding with just less than the voltage on line 529 requiredfor 360 phase shift.

Thus far, it has been assumed that the total phase shift required isless than 360. This generally is not the case and this fact is the basisfor including the second counter 519. More particularly, with the outputfrom the voltage ladder 517 fed to the comparator 533 and with thereference voltage from source 530 slightly less than the voltagenecessary for a 360 phase shift, when the ladder output voltage exceedsthe voltage from source 530, the counter 518 will be reset. However,with the clock pulse being applied thereto, counter 518 will repeat itscycle so long as the clock pulse train is present. In contrast, thecounter 519 continues its count until the clock pulse train is stoppedby disabling gate 522. In this way, the output of the ladder 517 alwaysindicates a phase shift in the range of to 360. Counter 519 alwayscontains the number of the columns in binary form for which the voltagebeing generated at that instant applies.

The sample-and-hold units may be of conventional construction involvingclosure of a switch in response to a given voltage state on a decoderoutput line, such as line 520i. This charges a capacitor in thesample-and-hold unit 532i such that the voltage on the output line fromunit 532i is equal to the input voltage on bus 531 at the instant ofclosure of the switch. With a high impedance output bufferamplifier inthe sample-and-hold units, the charge on the condenser will remainunchanged after the input switch is opened. Switches in thesample-and-hold units are controlled by the decoded state of counter519, as above noted. State 1 of counter 519 closes the switch in thesampleand-hold units 532i and 5421'. Since the inverter 540 is employedto feed bus 541, the two voltages are thus stored as reference voltagesfor two phase shift units. When the counter 519 reaches its nth state, avoltage for each column is stored in the Zn sample-and-hold units. Thedecoded nth state of counter 519 also resets unit 523 and ends theprocess.

The controller 550 for the rows of antenna modules is identical to thecontroller 510 for the columns of antenna modules. If the rows andcolumns are the same in number, then the controllers are identical. Ifthe rows and columns are not the same, then the controllers differ onlyin the number of states produced by the counter 519.

The phase shift reference voltage, for application to a given module, isproduced by summing the voltages from two of the sample-and-hold units.This would be accomplished by means of a pair of summing resistances foreach element, such as resistances 560 and 561. The output voltage fromunit 552i would be separately summed with each of the output voltagesfrom the sample-andhold units 532i-532n and 542i542n.

It is not necessary that the antenna be as shown in FIGURE 23. Byomitting elements in the outer rows or columns, the configuration shownin FIGURE 1 may be formed. Entire rows or entire columns may be omitted,depending upon the particular application required. If only one columnis employed or if only one row is employed, then either the unit 510 orthe unit 550 would be employed to generate the phase control referencevoltages.

Time sequence In FIGURE 25 Time Graphs IXII illustrate the operation ofthe system. Graphs IV represent the operation of the delay line phasecontrol network and Graphs VI-XII are system timing functions.

The voltage shown on Graph I represents the voltage at the input to thevoltage comparator 143, namely the reference voltage applied to terminal35. The voltage of Graph II is a reset pulse applied to the counters(not shown) to reset the circuits including switches SWl-SW6 to zeroupon the appearance of a reference voltage at terminal 35 which ischanged from any previous value.

The voltage on Graph III represents the voltage at the output of theconverter 153 and applied to the voltage comparator 143. This voltageappears on line 154.

The wave form shown on Graph IV represents the output voltage appearingat the output of the voltage comparator 143. The voltage represented byGraph V represents the output pulses passing through the AND gate 142and appearing on the input line 140 to the SW-l, which is the firststage in the 9-bit ripple-through phase shift counter.

In operation, when the phase shift counter is reset, the output voltagefrom the analog converter 153 drops back to zero and then as the delaylines are switched into the circuit by operation of the switchesSWI-SW6, the voltage on line 154 builds up until it equals the value ofthe reference voltage on terminal 35 at which time the switching circuitceases to change state by reason of the fact that the AND gate 142 isthen disabled.

Graph VI illustrates the state of the transmit-receive switches. Moreparticularly, the voltage of the master trigger shown on Graph V1 isapplied to the control input terminal of the multivibrator 163. Thepulse 6a shown in FIGURE 4 actuates a gate circuit so that transmitswitches 162, 137 and will be conductive and receive switches 164, 138and 121 will be nonconductive. During the remainder of each TR cycle,the receive switches 164, 138 and 121 will be conductive.

Graph VII illustrates the variation in the frequency control voltagegenerated by the pulse compression generator 44 of FIGURE 3. Thefrequency control voltage is applied to the oscillator 41 to vary thefrequency from a low frequency to a high frequency over a band of 1.25me. The resultant output of the oscillator 41 is illustrated by GraphVIII. The compression modulated pulse appears at the output of the poweramplifier frequency modulated over a range of 1.25 me. However, as theantenna excita-

